PrecisionClock-Hardware

PCB design for the Precision Clock
git clone https://git.mitxela.com/PrecisionClock-Hardware.git
Log | Files | Refs | README

Branches

Name Last commit date Author
master2019-05-04 12:07:12 +0100mitxela

Tags

Name Last commit date Author
pcbway-2018-08-222018-08-22 20:37:27 +0100mitxela
pcbway-2018-09-182018-09-18 13:38:14 +0100mitxela
pcbway-2019-02-222019-02-22 18:28:43 +0000mitxela
v1

File Tree (HEAD)

Name Size
.gitattributes140B
.gitignore12B
3d_models/7segDigit.wrl111.1K
3d_models/BarrelJack.wrl145.5K
3d_models/Capacitor_THT.3dshapes/C_Disc_D3.0mm_W1.6mm_P2.50mm.wrl30.84K
3d_models/Capacitor_THT.3dshapes/C_Disc_D5.0mm_W2.5mm_P5.00mm.wrl38.59K
3d_models/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x02_P2.54mm_Vertical.wrl15.06K
3d_models/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x05_P2.54mm_Vertical.wrl33.96K
3d_models/LED_THT.3dshapes/LED_D3.0mm.wrl35.28K
3d_models/OptoDevice.3dshapes/R_LDR_4.9x4.2mm_P2.54mm_Vertical.wrl47.21K
3d_models/Package_DIP.3dshapes/DIP-20_W7.62mm.wrl141.3K
3d_models/Package_DIP.3dshapes/DIP-24_W7.62mm.wrl150K
3d_models/Package_TO_SOT_THT.3dshapes/TO-92_Inline.wrl20.88K
3d_models/Potentiometer_THT.3dshapes/Potentiometer_Trimmer_Piher_PT-6v_Horizontal.wrl237.4K
3d_models/Resistor_THT.3dshapes/R_Axial_DIN0207_L6.3mm_D2.5mm_P7.62mm_Horizontal.wrl95.62K
7SegDigit.scad1.737K
7seg1inchCC.kicad_mod6.594K
7segcc.pretty/7seg1inchCC.kicad_mod1.623K
7segcc.pretty/7segcc.pretty/7seg1inchCC.kicad_mod1.659K
AD-121F2.kicad_mod4.4K
BarrelJack.scad1.233K
BarrelJack_2.kicad_mod2.45K
LED_D3.0mm.kicad_mod1.229K
README.md85B
barrel_jack.bck221B
barrel_jack.dcm221B
barrel_jack.lib633B
clock_mkiii_dst.mdr13.11K
convertSTL.rb3.892K
fp-lib-table102B
logo.kicad_mod51.5K
logo.png24.89K
logo.svg43.42K
power in.bck36.95K
power in.dcm36.95K
power in.lib390.6K
precision clock-cache.bck48B
precision clock-cache.dcm48B
precision clock-cache.lib11.77K
precision clock-rescue.bck51B
precision clock-rescue.dcm51B
precision clock-rescue.lib7.978K
precision clock.kicad_pcb699.8K
precision clock.net12.12K
precision clock.pro679B
precision clock.sch40.18K
precision clock.xml34.25K
rescue-backup/precision clock-2018-07-31-22-00-32.pro1.22K
rescue-backup/precision clock-2018-07-31-22-00-32.sch31.28K
rescue-backup/precision clock-2018-08-07-20-23-16.pro679B
rescue-backup/precision clock-2018-08-07-20-23-16.sch31.28K
rescue-backup/precision clock-cache-2018-07-31-22-00-32.lib7.938K
rescue-backup/precision clock-cache-2018-08-07-20-23-16.lib7.938K
rescue-backup/precision clock-rescue-2018-08-07-20-23-16.lib5.235K
rescue-backup/sym-lib-table-2018-08-07-20-23-16139B
sym-lib-table235B

History

* 1c78a9b (HEAD -> master) | mitxela 2019-05-04 12:07 | Remove outdated gerber files | * 2cb4c41 | mitxela 2019-05-04 12:03 | Add readme | * d772b59 | mitxela 2019-05-03 22:37 | Add .gitattributes file | * 67d9463 (origin/master, origin/HEAD) | mitxela 2019-04-02 23:29 | Add moshidraw vector file to repo | * 3af1d5f (tag: pcbway-2019-02-22) | mitxela 2019-02-22 18:28 | Update silkscreen | * 691e615 | mitxela 2019-02-22 14:59 | Add cuttable trace to make LDO optional | * bd6587e | mitxela 2019-02-22 13:05 | Optimize routing and fix drc errors | * b5bb90f | mitxela 2019-02-22 12:29 | Add optional footprint for crystal | * f4b4531 | mitxela 2019-02-22 10:48 | Add revision number | * 7b08d49 | mitxela 2019-02-22 01:05 | Add decoupling caps to display drivers | * 5ea9683 | mitxela 2019-02-21 23:50 | Add dummy logo to schematic | * 6994424 | mitxela 2019-02-21 23:37 | Alter LDR footprint to show value, not reference | * 0917375 | mitxela 2019-02-21 22:56 | Update schematic to match PCB | * 82972b9 | mitxela 2019-02-21 22:54 | Remove more backup files from repo | * 42c9a78 | mitxela 2019-02-21 20:55 | Align corner vias | * 809b7be | mitxela 2019-02-21 20:54 | Revert "Remove ground plane around GPS module" | * 659e028 (tag: pcbway-2018-09-18) | mitxela 2018-09-18 13:34 | Remove ground plane around GPS module | * 77bc3b0 | mitxela 2018-09-10 14:40 | Move colons to rotationally symmetric positions | * e30de70 | mitxela 2018-09-10 13:03 | Widen TO-92 footprints, update silkscreen, move vias out of logo | * 7e6f543 (tag: pcbway-2018-08-22) | mitxela 2018-08-22 20:37 | Another tiny routing change, get rid of long thin ground bit on the left | * 2f3097b | mitxela 2018-08-21 14:44 | Swap GPS data and VDD lines (purely aesthetic) | * e932df1 | mitxela 2018-08-21 01:18 | Some very trivial routing changes | * c580817 | mitxela 2018-08-21 00:47 | Move logo over a little to be more centred | * d82ce15 | mitxela 2018-08-21 00:37 | Move barrel jack westwards by 22mm | * d2fd86e | mitxela 2018-08-21 00:37 | stop tracking backup file | * 91c48f9 | mitxela 2018-08-20 23:30 | Move DST LEDs very slightly closer together | * 9a91c6e | mitxela 2018-08-20 23:06 | Controversial change to routing along the bottom of front copper. Removes some of the triangles and stops the ground plane from having little cutout bits | * d15de6c | mitxela 2018-08-20 22:56 | Add 3d model for potentiometer, found in the 'old' kicad libraries on github | * df1bd7f | mitxela 2018-08-20 22:42 | Remove extra mounting holes, light changes to routing around attiny | * d74d283 | mitxela 2018-08-20 22:40 | D'oh! fixed paths for 3D models | * 5587f04 | mitxela 2018-08-20 22:23 | Change the barrel jack icon to not give an error when exporting vrml file | * f38ef8c | mitxela 2018-08-20 22:13 | Move all 3D models to project folder | * cf623f0 | mitxela 2018-08-20 20:15 | Load 3D model for 7 seg display | * a301410 | mitxela 2018-08-20 20:13 | Load 3D model for barrel jack | * 08915ad | mitxela 2018-08-20 20:10 | Add 3D files for 7seg display and barrel jack | * 128318d | Tom Spurling 2018-08-20 19:57 | Attempt to add mounting holes and clear jack from edge | | * f567d96 (origin/3dstuff) | | mitxela 2018-08-20 13:55 | | Mucking about with 3D stuff | | | * f4415d3 |/ mitxela 2018-08-19 22:54 | Edit circle in barrel jack diagram to not give an error when exporting vrml file | * 5e07a3e (tag: v1) | Tom Spurling 2018-08-19 00:51 | Gerbors | * ef6c0f1 | Tom Spurling 2018-08-19 00:50 | Move everything to not have co-ordinates less than zero | * 124d9b0 | Tom Spurling 2018-08-18 14:42 | Move ATTiny to be entirely under displays | * 59e5f7c | Tom Spurling 2018-08-18 14:17 | Insert logo and credits on board | * 49fd88d | Tom Spurling 2018-08-18 14:17 | logo | * 238518b | mitxela 2018-08-18 13:42 | Silk screen work | * eaf03fe | Tom Spurling 2018-08-18 11:20 | Correct 7seg library to not have silk screen at edge | * 72aea1b | Tom Spurling 2018-08-18 11:20 | Edge cuts | * b5802ae | Tom Spurling 2018-08-18 10:24 | Align floods with outermost track | * b259850 | mitxela 2018-08-18 03:13 | All routing done! | * b253ad7 | mitxela 2018-08-18 01:33 | Most routing done | * 6fd5501 | mitxela 2018-08-17 21:57 | Routing begins! | * f10cf2e | mitxela 2018-08-07 23:24 | Components positioned | * 05f7e41 | mitxela 2018-08-07 22:11 | NO WARNINGS | * cade98a | mitxela 2018-08-07 20:21 | After opening in kicad 5.0.0 | * d23e5c8 Tom Spurling 2018-07-31 05:17 Schematic; no PCB

Contents of README.md:

PCB design for the Precision Clock Mk III

TODO: